HI5746 is a 10-bit monolithic analog-to-digital converter fabricated in CMOS process. It is critical for power consumption for broadband and low-bandwidth high-speed applications. Its 40MSPS speed is achieved through a completely different pipeline structure with an internal sample and hold. The HI5746 has excellent dynamic performance while consuming only 225mW at 40MSPS. The data output provides a latch that provides a valid data bus to the output with a delay of 7 clock cycles. It is functionally compatible with HI5702 and HI5703.

feature

Sampling Rate. 8.8 bits in 40ms, low power at fIN=10MHz 40MSPS. 225 MW wide full power input bandwidth. 250 MHz on-chip sample and hold fully differential or single-ended analog input single supply voltage. +5V TTL/CMOS compatible digital input CMOS compatible digital output. 3.0/5.0 Volt Offset Binary or Two's Complement Output Format Lead-Free Available

application

Professional Video Digitization

medical imaging

digital communication system

High-speed data acquisition

Absolute Maximum Ratings TA=25 oC Thermal Information

Supply voltage, AVCC or DVCC to AGND or DGND. 6 volts

DGND to AGND. 0.3V

Digital I/O pins. DGND to DVCC

Analog input/output pins. AGND to AVCC

operating conditions

temperature range

HI5746KCB (typ.). 0oC to 70oC

Thermal Resistance (Typical, Note 1) θJA (oC/W)

SOIC package. 70

SSOP package. 100

maximum junction temperature. 150 degrees Celsius

Maximum storage temperature range. -65 degrees Celsius to 150 degrees Celsius

Maximum lead temperature (10s for soldering). 300 degrees Celsius

(SOIC, SSOP - lead only)

CAUTION: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a pressure rating and operation

Note:

1. θJA is measured in free air with components mounted on the evaluation PC board.

Electrical Specifications AVCC=DVCC1=5.0V; DVCC2=3.0V, VREF+=2.5V; VREF-=2.0V; fS=40 MSPS, 50% duty cycle; CL=10pF; TA=25oC; differential analog input; typical value Test results at 25oC unless otherwise specified

Electrical Specifications AVCC=DVCC1=5.0V; DVCC2=3.0V, VREF+=2.5V; VREF-=2.0V; fS=40 MSPS, 50% duty cycle; CL=10pF; TA=25oC; differential analog input; typical value Test results at 25oC unless otherwise specified (continued)

notes:

2. Parameters guaranteed by design or characterization, not production tested.

3. Low clock and DC input.

notes:

4.SN: Nth sampling period.

5.HN: The Nth holding period.

6. BM, N: The M-th digital output corresponding to the N-th sampled input.

7.DN: The final data output corresponding to the Nth sampled input.

Detailed explanation of the theory of operation

The HI5746 is a 10-bit fully differential sampling pipeline a/D converter with digital error correction logic. Figure 25 depicts the front-end differential input differential output sample-and-hold circuit (S/H). The switch is internally controlled by the non-overlapping two-phase signal sampling clocks 1 and 2, from the main sampling clock. During the sampling phase, 1, the input signal is applied to the sampling capacitor, CS. At the same time, the capacitor, CH, discharges to analog ground. The input signal samples the capacitor on the sampling backplane on the falling edge of 1. In the next clock stage, the two backplane sampling capacitors are connected together and the hold capacitor is switched to the op amp output node. The charge is then redistributed between CS and CH completing for one sample-and-hold cycle. The front-end sample and hold outputs are analog inputs. The circuit not only performs the sample and hold function, but also converts the single-ended input to the fully differential output of the converter core. During the sampling phase, the VIN pin only sees the switch and CS. The relatively small values of these components result in a typical full power input bandwidth of the converter of 250MHz.

As shown in the functional block diagram and timing diagram in Figure 1, eight identical pipeline sub-converter stages, each containing a two-bit flash converter and a 2-bit multiplying digital-to-analog converter, follow the S/H stage nine A circuit for a two-bit flash converter. Each converter stage in the pipeline will amplify in one phase and amplify in the other clock phase. Each single subconverter clock signal is offset 180 degrees from the stage in the previous stage clock signal generation pipeline that performs the same operation. The output stages of the eight identical two-bit converters are a two-digit word containing a complement bit for digital error correction logic. The output of each sub-converter stage is input to a digital delay line controlled by an internal sampling clock. The functional digital delay line is an 18-bit result on eight digital error correction logic corresponding to the output of the ninth stage before applying the flash converter. This digital error correction logic uses supplementary bits to correct any errors that may exist in the converter's digital data output before generating the last ten bits. Due to the pipelined nature of this converter, the data representing the analog input samples digitally is output to the digital data bus for analog samples after the seventh clock cycle. This time delay is designated as the data delay. After the data delay time, the digital data representation outputs each subsequent analog sample in the next clock cycle. The digital output data is synchronized with the external sampling clock by a double-buffered latch technique. The output correction circuit for digital errors has two's complement or offset binary format depending on the state select (DFS) control input of the data format (see Table 1, A/D Code Table). Voltage Reference Inputs, VREF- and VREF+ The HI5746 is designed to accept two external reference voltage sources at the VREF input pin. Typical operation of the converter requires VREF+ to be set to +2.5V and VREF- to be set to 2.0V. However, it should be noted that the structure of the input VREF+ and VREF- input pins consists of a resistor divider with a resistor divider (nominal 500) connected to VREF+ and VREF- and another resistor of the voltage divider (nominal 500) 2000) between VREF- and analog ground. This allows the user to provide only the option of +2.5V VREF+ voltage reference +2.0V VREF- by the voltage divider of the input structure. Testing the HI5746+ with VREF- equal to +2.0V and VREF equal to +2.5V yields a fully differential analog input voltage range of ±0.5V. VREF+ and VREF- may be different voltages from the above (see Typical Performance Curves, Figure 8 through Figure 13). To minimize the overall noise of the inverter, it is recommended to provide sufficient high frequency decoupling of the VREF+ and VREF- voltage reference input pins in two locations. Analog Input, Differential Connection The analog input of the HI5746 is a differential input that can be configured in different ways depending on the signal source and desired performance level. Fully differential connections (Figure 26 and Figure 27) will give the best performance from the converter.

Since the HI5746 is powered by a +5V analog supply, the analog input is limited between ground and +5V. For differential input connections, this means that the analog input common mode voltage ranges from 0.25V to 4.75V. The performance of the ADC does not change much from the analog input common-mode voltage value. A DC voltage source, VDC, equal to 3.2V (typ) can help simplify circuit design when the user uses an AC-coupled differential input. This low output impedance voltage source is not designed as a reference, but is an excellent DC bias source and remains within the analog input common-mode voltage range over temperature (see Typical Performance Curves, Figure 21). For AC-coupled differential inputs (Figure 26), assume VREF+ (typically 2.5V) and VREF-, typically 2.0V, and 0.5V. When the VIN and -VIN input signal is 0.5VP-P, where -VIN is 180 degrees inconsistent with the VIN. The converter will VDC+0.25V when the VIN+ input is at positive full scale, and the VIN input is VDC-0.25V (VIN+-VIN-=+0.5V). Instead, the converter will be at negative full scale -0.25 volts when VIN + input equals VDC, VIN - at DC +0.25 volts (VIN + - VIN - = -0.5 volts). The analog input can be DC coupled (Figure 27) as long as the input is within the range of the analog input common-mode voltage range (0.25VVDC4.75V).

Resistor R in Figure 27 is not strictly necessary but can be used as a load setting resistor. A capacitor, C, connected from VIN+ to VIN- will help filter out any high-value pairs of frequency noise on the input, also improving performance. A value around 20pF is sufficient for AC coupled inputs as well. However, note that the choice of capacitor C must take into account the frequency components of the analog input signal. Analog Inputs, Single-Ended Connections The configuration shown in Figure 28 can be used with single-ended AC-coupled inputs.

Again, assume the difference between VREF+, which is typically 2.5V, and VREF-, which is typically 2V, is 0.5V. If the VIN is a 1VP-P sine wave, then VIN+ is a 1VP-P sine wave with a positive voltage equal to VDC. The converter will be in positive full scale when VIN+ is VDC+0.5V (VIN+VIN), when VIN+ is equal to VDC-0.5V (VIN+VIN) No.+-VIN-=-0.5V). Enough headroom must be provided so that the input voltage never goes above +5V or below AGND. In this case, the VDC may be between 0.5V and 4.5V with no noticeable change in ADC performance. The easiest way to produce VDC is to use a DC bias source, VDC, to output the 5746. A single-ended analog input can be DC-coupled (Figure 27) as long as the input is within the common-mode voltage range of the analog input.

Resistor R in Figure 29 is not strictly necessary, but can be used as a load setting resistor. A capacitor, C, connected from VIN+ to VIN- will help filter out any high-value pairs of frequency noise on the input, also improving performance. A value around 20pF is sufficient for AC coupled inputs as well. However, note that the choice of capacitor C must take into account the frequency components of the analog input signal. A single-ended source can provide better overall system performance if it is driving the HI5746. Digital output control and clock requirements HI5746 provides a standard high-speed interface to external TTL logic family. To ensure the rated performance of the HI5746 the clock cycle should be kept at 50%±5%. It must also have low jitter and operate at standard TTL levels. The performance of the HI5746 is only at conversion rates higher than 1 MSPS. This ensures the performance of the internal dynamic circuitry. Likewise, when power is first applied to the converter, a maximum of 20 cycles with sample rates above 1 MSPS must be performed before valid data is available. A Data Format Select (DFS) pin is provided which will determine the format of the digital data output. When at logic low, data will be output in offset binary format. When logic high, data will be output in 2's complement format.

notes:

8. The voltages listed above represent the ideal center of each output code as a function of the reference differential voltage, (VREF+-VREF-)=0.5 volts.

9. VREF+=2.5V and VREF-=2V.

When pulled high, the output enable pin, OE, will be a three-state digital output to a high-impedance state. Set to run experience normal operation logic low input.

Power and Grounding Considerations

The HI5746 has separate analog and digital power supplies, and ground pins, preventing digital noise paths in the analog signal. The digital data output also has a separate power supply pin, DVCC2, which can be powered from a 3V or 5V supply. If so, this allows the output to interface with the 3V logic desired. This part should be installed where power and ground are provided for analog and digital. For best performance the supply of HI5746 should be controlled by a clean linear drive. The board should also have a good height mounted as close to the converter as possible. If the part is powered off then the analog power supply should be combined with the ferrite beads from the digital power supply. Converters" (AN9214) for use in high-speed converters. Static performance defines the offset error (VOS) mesoscale transcoding should occur at the 1/4 LSB level over half a scale. The offset is defined from this point on Actual code transition. Full-scale error (FSE) The last code transition should occur when the analog input falls below positive full-scale (+FS) 3/4 LSB removes the error. Full-scale error is defined as the actual code from this point on Conversion. Differential Linearity Error (DNL) DNL is the code width from the ideal value of 1 LSB. Integral Linearity Error (INL) INL is the worst-case deviation between the code center and the best code center Fit a straight line based on measured data. Power Sensitivity Each power supply is shifted by plus or minus 5% offset and full scale error (LSB) offset for attention. Dynamic Performance Definition Fast Fourier Transform (FFT) technique is used to evaluate the dynamic performance of the HI5746. Low distortion sine wave is applied to the input, it is sampled consistently, and the output is stored in RAM. The data is then converted to frequency domain analysis using FFT to evaluate the dynamic performance of the A/D. A sine wave input is fractionally more than full for all of these tests The scale is -0.5dB lower.

SNR and SNR are expressed in decibels. Distortion figures are quoted in dBc (decibels) including all correction factors for normalization to full scale. Effective number of digits (ENOB) The effective number of digits (ENOB) is based on SINAD data: ENOB=(SINAD-1.76+VCORR)/6.02, where: VCORR=0.5dB. VCORR is the analog input signal below full scale. Signal-to-Noise Ratio and Distortion Ratio SINAD is the ratio of the measured RMS signal to the RMS sum of all other spectral components below the Nyquist frequency, fS/2, excluding DC. Signal-to-Noise Ratio SNR is the ratio of the measured RMS signal to the RMS noise at a specified input and sampling frequency. Noise is the rms of all spectral components below fS/2 and excluding fundamental, first 5 harmonics and DC. Total Harmonic Distortion (THD) THD is the ratio of the root mean square sum of the first 5 harmonics to the RMS value of the basic input component signal. Second and Third Harmonic Distortion This is the ratio of the rms value of the applicable harmonic components to the rms value of the fundamental input signal. Spurious Free Dynamic Range (SFDR) SFDR is the fundamental rms amplitude of the spectrum with the rms amplitude of the next largest spectral component below fS/2. Non-linearities in the intermodulation distortion signal path will tend to arise when two tones f1 and f2 appear at the input. The signal is measured and the distortion term is calculated. Included in the calculations are (f1+f2), (f1-f2), (2f1), (2f2), (2f1+f2), (2f1-f2), (f1+2f2), (f1-2f2). The ADC is tested with 6dB per tone below full scale. Transient Response The transient response measures the number of cycles required to convert the analog input to the ADC and measure the output code by providing full scale with 10-bit accuracy. Overvoltage recovery Overvoltage recovery provides a full-scale conversion to the ADC's analog input input of 200 mV, measuring the number of cycles to make the output code accurate to within 10 digits

Full Power Input Bandwidth (FPBW) Full power input bandwidth is the digitally reconstructed output whose amplitude is 3dB lower than the input sine wave amplitude. The amplitude of the input sine wave is from -FS to +FS. The given bandwidth is at the specified sampling frequency. Video Definitions Differential gain and differential phase are usually two of the ranges found in an ADC that describe the offset of the chrominance signal through the input voltage. Differential Gain Differential Gain is the peak difference in chrominance relative to the amplitude (percentage) of the reference burst. Differential Phase (DP) Differential Phase is the phase (in degrees) of the peak difference in chrominance relative to the reference burst. Timing Definitions See Figure 1 and Figure 2 for these definitions. Aperture Delay (Tap) Aperture delay refers to the external sample command (falling edge of the clock) and the actual sampling point of the time signal. This delay is due to internal clock path propagation delays. Aperture Jitter (Taj Mahal) Aperture jitter is due to variations in internal clock path delays. Data Hold Time (tH) Data Hold Time is the time when the previous data (N-1) arrives no longer valid. Data Out Delay Time (tOD) Data Out Delay Time is the time (N) that new data arrives to be valid. Data Latency (tLAT) After the analog samples are acquired, the digital data represents the 7th cycle of the clock after the analog input samples are output to the digital data bus analog sampling. This is due to the pipelined nature of the converter, where analog samples must pass through internal subconverter stages. This delay is designated as data delay. After the data delay time, representing each subsequent analog sample in the following output clock cycles. The digital data lags the analog input samples by 7 sample clock cycles. Power-On Initialization This time is defined as the maximum number of clock cycles required to initialize the converter at power-up. This requires initialization of the circuitry within the dynamic converter.