feature

Two integrated zero-drift, rail-to-rail, chopper amplifiers; TEC voltage and current operation monitoring; programmable TEC maximum voltage and current Programmable TEC current heating and cooling limits; configurable switching frequency up to 1 MHz Power efficiency: >90% ; temperature lock indication; selectable internal or external clock source; clock phase adjustment for multi-drop operation; supports negative temperature coefficient (NTC) thermistor or positive temperature coefficient (PTC) resistance thermal detector (RTD); 5 V typical and optional 3 V power supply; standby and shutdown mode availability; adjustable soft-start function; 5 mm x 5 mm 32-lead LFCSP.

application

Thermoelectric cooler temperature control; DWDM optical transceiver modules; fiber amplifiers; optical network systems; instruments that require TEC temperature control.

General Instructions

The ADN8831 is a monolithic TEC controller. It has two integrated, zero-drift, rail-to-rail comparators and a PWM driver. The unique PWM driver works with the analog driver to control the external select mosfet in the H-bridge. By sensing thermal detector feedback from the TEC, the ADN8831 can drive the TEC to determine the programmable temperature of a laser diode or passive component connected to the TEC module.

The ADN8831 supports NTC thermistors or positive temperature coefficient (PTC) RTDs. The target temperature is set to the analog voltage input from the DAC or an external resistor divider driven by a reference voltage source.

A proportional-integral-derivative (PID) compensation network helps stabilize the ADN8831 thermal control loop quickly and accurately. An example of a tunable PID compensation network is described in An-695 Application Note ADN8831T. The ADN8831 provides a typical reference voltage of 2.5 V for thermistor temperature sensing or for measuring and limiting TEC voltage/current in cooling and heating modes.

Detailed block diagram

Absolute Maximum Ratings

Absolute Maximum Ratings at 25°C unless otherwise noted.

Stresses above the Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device under the conditions described in the operating section of this specification or any other conditions above is not implied. Long-term exposure to absolute maximum rating conditions may affect device reliability.

Thermal characteristics

θ is specified in the worst case, i.e., a device soldered in a circuit board in a surface mount package.

Typical performance characteristics

theory of operation

The ADN8831 is a single-chip TEC controller for setting and stabilizing the TEC temperature. The voltage applied to the input of the ADN8831 corresponds to the target TEC temperature setpoint (temperature setting). By controlling an external FET H-bridge, the appropriate current is applied to the TEC, pumping heat to and from objects attached to the TEC. The target temperature is measured by a thermal sensor connected to the TEC, and the sensed temperature (voltage) is fed back to the ADN8831 to complete the closed thermal control loop of the TEC. For optimal stability, the thermal sensor must be close to the object. In most laser diode modules, TEC and NTC thermistors are already installed in the same package to regulate the temperature of the laser diode.

The ADN8831 integrates two self-calibrating, auto-zeroing amplifiers (Chop1 and Chop2). The Chop1 amplifier typically takes a thermal sensor input and converts or regulates the input to a linear voltage output. The output 1 (pin 4) voltage is proportional to the target temperature. The output 1 (pin 4) voltage is fed into a compensation amplifier (Chop2) and compared to the temperature setpoint voltage, resulting in an error voltage proportional to the difference. When using the Chop2 amplifier, it is recommended to use a PID network as shown in Figure 12.

Tuning the PID network optimizes the step response of the TEC control loop. Once this is done, a compromise between settling time and maximum current ringing is obtained. See the PID Compensation Amplifier (CHOP2) section for details on how to tune the compensation network. TEC adopts H-bridge structure differential drive. The ADN8831 drives an external MOSFET transistor to provide the TEC current. To further improve the power efficiency of the system, a PWM driver is used on one side of the H-bridge. Only one inductor and one capacitor are needed to filter out the switching frequency. The other side of the H-bridge uses the linear output and does not require any additional circuitry. This proprietary configuration allows the ADN8831 to provide greater than 90% efficiency. The 4.7µH inductor, 22µF capacitor, and 1 MHz switching frequency maintain below 0.5% worst-case output voltage ripple on the TEC for most applications.

To set the maximum voltage and current flowing through the TEC using VLIM (pin 31) and ILIMC (pin 1)/ILIMH (pin 32). See the Maximum TEC Voltage Limit section and the Maximum TEC Current Limit section for more details.

Oscillator Clock Frequency

The ADN8831 has an internal oscillator to generate the switching frequency of the output stage. The oscillator can be set to free-running mode or synchronized to an external clock signal.

free running

The switching frequency is set by a resistor from FREQ (pin 13) to ground. Table 5 shows R for some common switching frequencies. For free running operation, connect the frequency sync I/SD (pin 16) and component (pin 17) to PVDD (pin 18).

The higher switching frequency reduces the voltage ripple across the TEC. However, high switching frequencies generate more power dissipation in the external transistors due to more frequent charging and discharging of the transistor gate capacitance.

External Clock Operation

The switching frequency of the ADN8831 can be synchronized to an external clock. Connect the clock signal to SYNCI/SD (pin 16) and connect COMOSC (pin 17) to the RC network. This network compensates the PLL to lock to the external clock.

Connecting Multiple ADN8831 Devices

Connecting SYNCO (pin 15) to the SYNCI/SD pin of another ADN8831 allows multiple ADN8831 devices to work together using a single clock. Multiple ADN8831 devices can be driven from a single master ADN8831 device by connecting the SYNCO pin of the master device to each slave SYNCI/SD pin, or by connecting the SYNCO pin of each device to the SYNCI/SD pin of the next device Daisy chain. When multiple ADN8831 devices are clocked at the same frequency, the phase is adjusted to reduce power supply ripple.

Oscillator Clock Phase

Use a simple resistor divider at phase (pin 10) to adjust the oscillator clock phase. Phase adjustment allows two or more ADN8831 devices to operate at the same clock frequency instead of switching all outputs simultaneously. This avoids the possibility of excessive power supply ripple.

To ensure proper operation of the oscillator, V should be kept in the range of 100 mV to 2.4 V. Phase (pin 10) is internally biased at 1.2 V. If the phase (pin 10) is left open, the clock phase is set to the default value of 180°. phase

temperature lock indicator

When the OUT1 (Pin 4) voltage reaches the IN2P (Pin 5) temperature set point (temperature set) voltage, the TMPGD (Pin 11) output is logic high. TMPGD has a detection range of ±25 mV with a typical hysteresis of 10 mV. This allows direct connection to a microcontroller or supervisory circuit.

boot soft start

The ADN8831 can be programmed for a specified time after power-on or after the SD pin is unplugged. This feature, known as soft-start, helps to gradually increase the duty cycle of the PWM amplifier. The soft-start time is set by a capacitor connected from SS (pin 14) to ground. The capacitor value is calculated according to the following formula: τ=150× where:

Where: CSS is the microfarad value of the capacitor; τSS is the soft-start time in milliseconds; to set the soft-start time to 15 ms, CSS is equal to 0.1 μF.

shutdown mode

Shutdown mode sets the ADN8831 to an ultra-low current state. Current consumption in shutdown mode is typically 8 microamps. Shutdown input SD (pin 16) is active low. To shut down the device, drive SD to logic low. Once a logic high is applied, the ADN8331 is reactivated after a time delay set by the soft-start circuit. See the Power-On Soft-Start section for more details.

Standby mode

The ADN8831 has a standby mode that turns off a MOSFET driver stage. In standby mode, the current consumption of the ADN8831 is less than 2 mA. Alternate input SS/SB (Pin 14) is active low. After applying a logic high, the ADN8331 reactivates after a delay. In standby mode, only SYNCO (pin 15) has a clock output. All other function blocks are closed.

TEC Voltage/Current Monitor

TEC real-time voltage and current were detected at VTEC (Pin 30) and ITEC (Pin 29), respectively.

voltage monitor

VTEC (pin 30) is an analog voltage output pin whose voltage is proportional to the actual voltage across the TEC. A center voltage of 1.25 V corresponds to 0 V across the TEC. The output voltage is calculated using the following formula:

Current monitor

ITEC (Pin 29) is an analog voltage output pin whose voltage is proportional to the actual current through the TEC. A central ITEC voltage of 1.25 V corresponds to 0 A through the TEC.

The output voltage is calculated using the following formula:

The formula for calculating the equivalent TEC current is as follows:

Maximum TEC Voltage Limit

The maximum TEC voltage is set by applying a voltage at VLIM (Pin 31) to protect the TEC. This voltage can be set by a resistor divider or DAC. The voltage limiter operates at bidirectional TEC voltage, cooling and heating voltages.

using DAC

When the voltage source directly drives VLIM (pin 31), the cooling and heating voltage limits are set at the same level. The maximum TEC voltage is calculated using the following formula:

Where: VTEC(MAX) is the maximum TEC voltage; VVLIM is the voltage applied to VLIM (Pin 31).

Use a resistor divider

Use resistor dividers to set individual voltage limits. When the ADN8831 drives the TEC in the heating direction, an internal current sink circuit connected to VLIM (Pin 31) draws current, reducing the voltage at VLIM (Pin 31). When the TEC is driven in the cooling direction, the current sink is not active; therefore, the TEC heating voltage limit is always lower than the cooling voltage limit.

The receiver current is set by a resistor connected from frequency (pin 13) to ground. Calculate the sink current using the following formula:

where: ISINC is the sink current at VLIM (Pin 31). RFREQ is a resistor connected to FREQ (pin 13).

The cooling and heating limits use the following equations:

Maximum TEC Current Limit

To protect the TEC, separate maximum TEC current limits are set in the cooling and heating directions by applying voltages across ILIMC (pin 1) and ILIMH (pin 32). The formula for calculating the maximum TEC current is as follows:

application information

signal flow

The ADN8831 integrates two auto-zero amplifiers, the Chop1 amplifier and the Chop2 amplifier. Both amplifiers can be used as stand-alone amplifiers, so the implementation of temperature control can vary. Figure 17 shows the signal flow through the ADN8831 and a typical implementation of a temperature control loop using the Chop1 and Chop2 amplifiers.

In Figure 17, the Chop1 and Chop2 amplifiers are configured as thermistor input amplifiers and PID compensation amplifiers, respectively. The thermistor input amplifier gets the thermistor voltage, which is then output to the PID compensation amplifier. The PID compensation amplifier then compensates the loop response in the frequency domain.

The output of the compensation loop at Output 2 is fed to the linear MOSFET gate driver. The voltage at LFB is fed into the PWM MOSFET gate driver through OUT2. Including external transistors, the gain of the differential output section is fixed at 5. See the MOSFET Driver Amplifier section for details on output drivers.

Thermistor Settings

Thermistors have a non-linear relationship with temperature; correlate the appropriate R value to the thermistor over the specified temperature range. First, the resistance of the thermistor must be known, where:

T low and thigh are the end points of the temperature range and TMID is the mean. In some cases, only the B constant is available, and the RTH is calculated using the following formula:

Where: RTH is the resistance at T[K]. RR is the resistance at TR[K]. The formula for calculating RX is as follows:

Thermistor Amplifier (Chop1)

The Chop1 amplifier can be used as a thermistor input amplifier. In Figure 17, the output voltage is a function of thermistor temperature. The voltage at OUT1 is expressed as:

Where: RTH is the thermistor. RX is a compensation resistor. R is calculated using the following formula:

VOUT1 is centered at VREF/2 at 25°C. Typical as shown in Figure 17, the average temperature to voltage ratio ranges from +5°C to +45°C with a factor of -25 mV/°C.

PID Compensation Amplifier (Chop2)

Use the Chop2 amplifier as a PID compensation amplifier.

The voltage at OUT1 is fed into the PID compensation amplifier. The frequency response of the PID compensation amplifier is determined by the compensation network. A temperature setting voltage is applied at IN2P. In Figure 17, the voltage at OUT2 is calculated using the following equation:

The user sets the precise compensation network. This network goes from simple integrator to PI, PID or any other kind of network. The user also determines the compensation type and component values as they depend on the thermal response of the object and TEC. One way to empirically determine these values is to input a step function to IN2P, which changes the target temperature, and adjust the compensation network to minimize the settling time for the TEC temperature.

A typical compensation network for laser module temperature control is a PID loop consisting of an extremely low frequency pole and two high frequency zeros. Figure 19 shows a simple network for implementing PID compensation. To reduce the noise sensitivity of the control loop, add an extra pole at frequencies above zero. The Bode plot of the magnitude is shown in Figure 20. The unity-gain crossover frequency of the feedforward amplifier is calculated using the following equation:

To ensure stability, the unity-gain crossover frequency should be lower than the thermal time constant of the TEC and thermistor. However, this thermal time constant is sometimes ambiguous, making it difficult to characterize. There are many articles on loop stabilization, and discussing all the methods and tradeoffs for optimizing compensation networks is beyond the scope of this data sheet.

Using the ADN8831-EVALZ board an-695, the application note shows how to determine the PID network components for stable TEC subsystem performance.

MOSFET driver amplifier

The ADN8831 has two independent MOSFET drivers: a switching output or pulse width modulation (PWM) amplifier and a high gain linear amplifier. Each amplifier has a pair of outputs that drive the gate of the external mosfet, which in turn drives the TEC, as shown in Figure 17. Monitor the voltage on the TEC via SFB (pin 23) and LFB (pin 27). While these two MOSFET drivers achieve the same result, providing constant voltage and high current, their operation is different. The exact equations for these two outputs are:

Where: VOUT2 is the voltage at OUT2 (pin 7). VB is determined by VDD as:

The voltage at OUT2 (Pin 7) is determined by compensation from the network input amplifier that receives the temperature setting voltage and the thermistor. The lower limit of VLFB is 0 V and the upper limit of VDD. Figure 21 shows these equations.

Dimensions