General Instructions

The AOZ1050PI is a high-efficiency, easy-to-use 2A synchronous buck regulator. The AOZ1050PI operates over an input voltage range of 4.5V to 18V , provides up to 2A of continuous output current, and the output voltage is adjustable down to 0.8V.

The AOZ1050PI is housed in an exposed pad SO-8 package and is rated for an ambient operating temperature range of -40°C to +85°C.

feature

4.5 V to 18 V operating input voltage range; synchronous buck: 80 mΩ internal high-side switch and 50 mΩ internal low-side switch at 12 V; up to 95% efficiency; external soft-start; output voltage adjustable to 0.8 V; 2 A continuous output current; 500 kHz pulse width modulation operation; cycle-by-cycle current limit; pre-bias start-up; short-circuit protection; thermal shutdown; exposed pad SO-8 package.

application

Point-of-load DC/DC converters; LCD TVs; set-top boxes; DVD and Blu-ray players/recorders; cable modems.

typical application

Ordering Information

OS green products use reduced halogens and are also RoHS compliant.

Pin configuration

Pin Description

block diagram

Absolute Maximum Ratings

exceed the absolute maximum ratings of the device.

Notes: 1. The device itself is ESD sensitive and requires handling precautions. Human body model grade: 1.5 kΩ in series with 100 pF.

Recommended Operating Conditions

Equipment is not guaranteed to exceed maximum recommended operating conditions.

NOTE: The value of 2.Θ is youth achievement measured with 2 oz copper mounted on a 1 inch FR-4 board in a still air environment at T = 25°C. The value in any given application depends on the user's specific board design.

Typical performance characteristics

The circuit of Figure 1. T=25°C, V=V=12 V, V=3.3 V, unless otherwise specified.

efficiency

Detailed description

The AOZ1050PI is a current-mode buck regulator that integrates a high-side PMOS switch and a low-silicon NMOS switch. The AOZ1050PI operates over an input voltage range of 4.5 V to 18 V and provides up to 2 A of load current. Features include enable control, power reset, input undervoltage lockout, output overvoltage protection, external soft-start and other shutdowns.

The AOZ1050PI has an exposed pad SO-8 package.

Enable and Soft Start

AOZ1050PI has xt rnal soft-start function to ensure that the output voltage rises and regulates the ion voltage smoothly. The soft-start process begins when the input voltage rises to 4.1V and the voltage on the pin is high. During the soft-start process, the FB voltage rises with the soft-start voltage pin until it reaches 0.8 V. The voltage on the soft-start pin is charged by an internal 5µA current.

The EN pin of AOZ1050PI is active high. If the enable function is not used, connect the EN pin to the VIN. Grounding EN will disable the AOZ1050PI. Don't leave the door open. The voltage on the EN pin must be higher than 2 V to enable the AOZ1050PI. When the EN pin voltage is below 0.6 V, the AOZ1050PI is disabled.

steady state operation

Under the steady state condition of heavy load, the converter works in constant frequency continuous conduction mode (CCM).

The AOZ1050PI integrates an internal P-MOSFET as a high-side switch. The inductor current is sensed by amplifying the voltage drop from the drain to the source of the high-side power MOSFET. The output voltage is reduced by an external voltage divider at the FB pin. The difference between the FB pin voltage and the reference voltage is amplified by an internal transconductance error amplifier. Compare the error voltage displayed on the COMP pin with the current signal at the input of the PWM comparator (that is, the sum of the inductor current signal and the slope compensation signal). If the current signal is less than the error voltage, the internal high side switch is turned on. Inductor current flows from the input through the inductor to the output. When the current signal exceeds the error voltage, the high side switch is turned off. The inductor current is free-wheeled for output through the internal low-side N-MOSFET switch. Internal adaptive FET drivers ensure that neither high-side nor low-side switches turn on overlap.

Compared to regulators that use free-spinning Schottky diodes, the AOZ1050PI uses free-spinning NMOSFETs for synchronous rectification. This greatly increases the efficiency of the converter and reduces the power loss in the low-side switch.

The AOZ1050PI uses a P-channel MOSFET as the high-side switch. This saves the bootstrap capacitance typically seen in circuits using NMOS switches. It also allows 100% opening of the high side switch for linear regulation mode of operation. The minimum voltage drop from V to V is the load current times the DC resistance of the MOSFET plus the DC resistance of the buck inductor. Its calculation formula is as follows:

where; V is the maximum output voltage, V is the input voltage from 4.5 V to 18 V, I is the output current from 0 A to 2 A, and R is the on-resistance of the internal MOSFET.

Output voltage programming

The output voltage can be set by feeding the output back to the FB pin using the resistor divider network shown in Figure 1. The resistor divider network consists of R and R. Typically, a design is started by picking a fixed value for R and calculating the required R using the following formula:

Some standard value output voltages of R1 and R2 of ost common are shown in Table 1.

The combination of R and R should be large enough to avoid drawing too much current from the output, which would result in power loss.

Since the switch duty cycle can be as high as 100%, the maximum output voltage can be set as high as the input voltage minus the voltage drop across the PMOS and inductor.

Protection features

AOZ1050PI has multiple protection functions to prevent system circuit damage under abnormal conditions.

Over Current Protection (OCP)

The sensed inductor current signal is used for overcurrent protection. Since the AOZ1050PI uses peak current mode control, the COMP pn voltage is proportional to the peak inductor current. The COMP pin voltage is internally limited between 0.4v and 2.5v. The peak current of the inductor is the automatic limit cycle.

When the output is shorted to ground under fault conditions, the inductor current decays slowly during switching cycle b, resulting in an output voltage of 0v.

To prevent catastrophic failure, a secondary current limit is designed inside the AOZ1050PI. The measured induced r-current is compared to a preset voltage (between 3.5 A and 5.0 A) that represents the current limit. When the output current is greater than the current limit, the high side switch will turn off. Once the overcurrent condition is resolved, the converter will initiate a soft start.

Power-On Reset (POR)

A power-on reset circuit monitors the input voltage. When the input voltage exceeds 4.1v, the converter starts to work. When the input voltage drops below 3.7V, the inverter will shut down.

Thermal Protection

An internal temperature sensor monitors the connector temperature. When the junction temperature exceeds 150°C, the sensor turns off the internal control circuit and the high-side PMOS. When the junction temperature drops to 100°C, the regulator will automatically restart under the control of the soft-start circuit.

application information

The basic AOZ1050PI application circuit is shown in Figure 1. Component selection is described below.

input capacitor

The input capacitor must be connected to the V pin and PGND pin of the AOZ1050PI to maintain a stable input voltage and filter out pulsed input current. The voltage rating of the input capacitor must be greater than the maximum input voltage plus the ripple voltage.

The input ripple voltage can be approximated by:

Since the input current of a buck converter is discontinuous, the current stress on the input capacitor is another consideration when choosing capacitors. For a buck circuit, the rms value of the input capacitor current can be calculated by the following formula:

If we let m equal the conversion ratio:

The relationship between the input capacitor rms current and the voltage slew rate is shown in Figure 2 below. It can be seen that the current stress of C is the largest when V is half of V. The worst current stress on C is 0.5x I.

For reliable operation and optimum performance, the input capacitor current rating must be higher than I would in worst case operating conditions. Ceramic Chinese input capacitors are preferred capacitors because of their low ESR and high current rating. Depending on the application circuit, other low ESR tantalum capacitors can be used. When choosing ceramic capacitors, X5R or X7R type dielectric ceramic capacitors should be used because they have better temperature and voltage characteristics. Note that the ripple current rating of the capacitor is based on a certain lifetime by the manufacturer. Further downgrades may require long-term consideration of term reliability.

sensor

The inductor is driven by the switching voltage to provide a constant current output. For a given input and output voltage, the inductor and switching frequency together determine the inductor ripple current, which is:

The peak inductor current is:

High inductance provides low inductor ripple current, but requires larger size inductors to avoid saturation. Low ripple current reduces inductor core losses. It also reduces the rms current through the inductor and switch, thereby reducing conduction losses. Typically, the peak-to-peak ripple current on the inductor is designed to be 20% to 40% of the output current.

When choosing an inductor, verify that it can handle peak current without saturation at the highest operating temperature. The inductor accepts the highest current in the buck circuit. Conduction losses on inductors need to be checked for thermal and efficiency requirements.

Coilcraft, Elytone and Murata offer surface mount sensors in different shapes and styles. The shielding inductance is small in size, and the radiated electromagnetic interference is small. However, they are more expensive than unshielded inductors. The choice depends on EMI requirements, price and size.

output capacitor

Select the output capacitor based on the DC output voltage rating, output ripple voltage specification, and ripple current rating.

The voltage rating of the selected output capacitor must be higher than the maximum expected output voltage (including ripple). Long-term reliability requires consideration of degradation.

The output ripple voltage specification is another important factor in selecting an output capacitor. In a buck converter circuit, the output ripple voltage is determined by the inductor value, switching frequency, output capacitor value, and ESR. It can be calculated by the following formula:

where C is the output capacitor value and ESR is the equivalent series resistance of the output capacitor.

When using a low ESR ceramic capacitor as the output capacitor, the impedance of the capacitor at the switching frequency dominates. The output ripple is mainly caused by the capacitor value and the inductor ripple current. The output ripple voltage calculation can be simplified as:

When the ESR impedance at the switching frequency dominates, the output ripple voltage is primarily determined by the capacitor ESR and inductor ripple current. The output ripple voltage calculation can be further simplified as:

For lower output ripple voltage over the entire operating temperature range, X5R or X7R dielectric ceramic, low ESR tantalum capacitors are recommended as output capacitors.

In a buck converter, the output capacitor current is continuous. The rms current of the output capacitor is determined by the peak-to-peak ripple current of the inductor. The calculation method is as follows:

Usually, the ripple current rating of the output capacitor is a lesser concern due to the low current stress. When the buck inductor is chosen to be small and the inductor ripple current is large, the output capacitor will be overstressed.

loop compensation

The AOZ1050PI uses peak current mode control for ease of use and fast transient response. Peak current mode control eliminates the bipolar effect of the output L&C filter. It also greatly simplifies the design of the compensation loop.

With peak current mode control, the buck power stage can be reduced to a frequency domain unipolar and a zero system. The pole is the dominant pole and can be calculated by the following formula:

The zero is the ESR z ro due to the output capacitance and its ESR. Its calculation method is as follows:

where; CO is the output filter capacitor, RL is the load resistance value, and ESRCO is the equivalent series resistance of the output capacitor.

The compensation design enables the converter control to shape the loop transfer function of the desired gain and phase. Several different types of compensation networks can be used with the AOZ1050PI. A capacitor and resistor network connected to the COMP pin sets the pole zero in most cases and is sufficient to stabilize the high bandwidth control loop.

In the AOZ1050PI, FB and COMP are the inverting inputs and outputs of the internal error amplifier. Series R and C compensation networks connected to COMP provide a pole and a zero. The rods are:

where; GEA is the error amplifier transconductance, which is 200 x 10-6 A/V, GVEA is the voltage gain of the error amplifier, which is 500v/V, and CC is the compensation capacitor in Figure 1.

The zero given by the external compensation network capacitor C and resistor R is located at:

To design the compensation circuit, the target crossover frequency f must be chosen to close the loop. The system crossover frequency is where the control loop has unity gain. Crossover is also known as converter bandwidth. Generally, higher bandwidth means faster response to load transients. However, considering the stability of the system, the bandwidth should not be too high. When designing the compensation loop, the stability of the converter under all line and load conditions must be considered.

In general, it is recommended to set the bandwidth equal to or less than 1/10 of the switching frequency.

The strategy for choosing R and C is to use R to set the crossover frequency and C to set the compensator zero. Calculate RC with the chosen crossover frequency f:

where: fC is the desired crossover frequency. For best performance, set fC to about 1/10 of the switching frequency; VFB is 0.8V, GEA is the error amplifier transconductance, which is 200×10-6a/V, and GCS is the transconductance of the current sense circuit, which is is 8 A/V.

Compensation capacitor CC and resistor RC combine to zero. This zero is placed somewhere close to the dominant pole fp1, but below 1/5 of the chosen crossover frequency. CC can be selected by:

The above equation can be simplified to:

An easy-to-use application software to aid in designing and simulating compensation loops can be found on .

Thermal Management and Layout Considerations

In the AOZ1050PI buck regulator circuit, high pulse current flows through two circuit loops. The first loop starts from the input capacitor, to the VIN pin, to the LX pad, to the filter inductor, to the output capacitor and load, and back to the input capacitor through ground. When the high-side switch is turned on, current flows in the first loop. The second loop starts from the inductor, to the output capacitor and load, to the low-side NMOSFET. When the low-side NMOSFET is turned on, current flows in the second loop.

In the PCB layout design, reducing the area of the two loops can reduce the noise of the circuit and improve the efficiency. It is strongly recommended to use a ground plane to connect the input capacitor, output capacitor and the PGND pin of the AOZ1050PI.

In the AOZ1050PI buck regulator circuit, the main power dissipation components are the AOZ1050PI and the output inductor. The total power dissipation of the converter circuit can be measured by subtracting the output power from the input power:

The power dissipation of the inductor can be approximated by the output current of the inductor and the DCR value:

The actual junction temperature can be calculated from the power dissipation in the AOZ1050PI and the thermal impedance of the junction to ambient:

The maximum junction temperature of the AOZ1050PI is 150°C, which limits the maximum load current capability.

The thermal performance of the AOZ1050PI is greatly affected by the PCB layout. Care should be taken during the design process to ensure that the integrated circuit operates under the recommended environmental conditions.

Layout Considerations

The AOZ1050PI is an exposed pad SO-8 package.

Some of the best electrical and thermal properties are listed below.

1. The exposed pad (LX) is connected to the internal PFET and NFET drains. Connect a large copper plane to the LX pin to help with heat dissipation.

2. Do not use thermal connections to the Vehicle Identification Number (VIN) pin or the PGND pin. Pour the largest copper area into the PGND pin and VIN pin to help with heat dissipation.

3. The input capacitor should be placed as close as possible to the VIN pin and the PGND pin.

4, the preferred ground plane. If no ground plane is used, separate PGND from AGND and connect at only one point to avoid PGND pin noise coupling to the AGND pin.

5. Keep the current trace from LX pad to L to Co to PGND as short as possible.

6. Pour copper planes on all unused board areas and connect them to stable DC nodes such as VIN, GND, or VOUT.

7. Keep sensitive signal traces away from the LX pads.

Package Dimensions, SO-8 EP1

notes:

1. The package size does not include mold flash and gate burr.

2. Dimension L is measured in the instrument plane.

3. Unless otherwise specified, the tolerance is 0.10 mm.

4. The control size is in millimeters, and the converted inch size is not necessarily accurate.

5. The exposure size of the die pad is designed according to the lead frame.

6. Connected from JEDEC MS-012.

Tape and Reel Dimensions, SO-8 EP1

part mark

life insurance policy

Alpha and Omega Semiconductor products are not authorized for use as critical components in life support devices or systems.

As used in this article:

1. A life support device or system means: (a) a device or system intended for surgical implantation in the body, or (b) intended to support or sustain life, and (c) when properly used in accordance with the instructions for use provided on the label , failure to do so could reasonably be expected to result in substantial harm to the user.

2. A critical component of any part of a life-saving appliance, device or system, the failure of which can reasonably be expected to cause the failure of the life-saving appliance or system, or to affect its safety or effectiveness.