The HIP6503 complements the HIP6020 or ACPI-compliant microprocessor and computer applications. The integrated circuit integrates four linear circuit controllers/regulators, switches, monitoring and control functions in a 20-pin SOIC package. A linear controller generates 3.3V dual/3.3V SB voltage planes from ATX to provide 5VSB outputs for Southbridge and PCI slot states (S3, S4/S5) via external transistors during sleep. The second transistor is used to turn on the ATX 3.3V output (active) operating state that operates during S0 and S1/S2. The linear controller/regulator has a selectable 2.5V or 3.3V memory supply to input the active state through an external pass transistor (3.3V set switch). In the sleep state, the integral provides sleep power through the transistor. The other controller switches the ATX 5V to 5V dual plane powered output active and the ATX5VSB in sleep. Two internal regulators output two dedicated, noise-free 2.5V clock chip supplies, and a 1.8V ICH2 recovery well voltage. The operating mode of the HIP6503 (active output or sleep output) can be selected via two digital control pins, S3 and S5. Enable sleep state support output on the EN5VDL pin on the 5V dual channel. The 3.3V dual/3.3V SB and 2.5V MEM/3.3V MEM linear regulators use an external N channel to output directly to the 3.3V input supply provided by the ATX power supply via a mosfet connection in active state to reduce losses. In sleep state, power on both outputs are routed to NPN transistors. Active state through an external NPN transistor. The 5V dual output is powered through two external MOS transistors. In the sleep state, the aPMOS (or PNP) transistor conducts current from the ATX 5VSB output; in the active state, the current conducts the NMOS transistor connected to the ATX 5V output. The operation of this 5V dual output is determined not only by the state of the S3 and S5 pins, but by the state of the EN5VDL pin as well. The 3.3V dual/3.3V SB and 1.8V SB outputs are active as long as the ATX5VSB voltage is applied to the chip. The 2.5V CLK output is only active during S0 and S1/S2 and uses the 3V3 pin as the input source element for the internal channel.

feature

Provides 5 ACPI Control Voltages - 5V Dual USB/Keyboard/Mouse - 3.3V Dual/3.3V SB PCI/Auxiliary/LAN - 2.5V Memory RDRAM or 3.3V Memory SDRAM - 2.5V Clock/Processor Terminal - 1.8V SB ICH2 Good recovery Excellent output voltage regulation - All outputs: Over temperature ±2.0% (where applicable) Small size; very low external component count Annealed (RoHS Compliant)

application

ACPI Compliant Motherboard Power Specifications

Absolute Maximum Ratings Thermal Information

Supply voltage, V 5VSB. +7.0V 12V. Ground -0.3V to +14.5V DLA, DRV2. Ground -0.3V to 12V +0.3V for all other pins. Ground -0.3V to 5VSB+0.3V ESD classification. Level 3

Recommended Operating Conditions

Supply voltage, V 5VSB. +5V±5% minimum 5VSB power supply voltage guaranteed parameters. +4.5 volt digital inputs, V SX, V EN5VDL. 0 to +5.5V ambient temperature range. 0°C to 70°C junction temperature range. 0°C to 125°C Thermal Resistance (Typical, Note 1) θJA (Celsius/Watt) SOIC Package (Note 1). 60

Maximum Junction Temperature (Plastic Packaging). 150 degrees Celsius

Maximum storage temperature range. -65°C to 150°C

Maximum lead temperature (10s for soldering). 300 degrees Celsius (SOIC - lead only)

CAUTION: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a pressure rating and operation of the device under the above or any other conditions stated in the operating section of this specification is not implied.

Note:

1. θJA is measured with components mounted on a high-efficiency thermal conductivity test board in free air.

Operating conditions recommended by electrical specifications, unless otherwise noted, refer to Figures 1, 2 and 3

Operating conditions recommended by electrical specifications, unless otherwise noted, refer to Figures 1, 2 and 3 (continued)

notes:

2. Sleep state only for 3.3V setting

3.5VSB<4.0V parameters are not guaranteed.

4. When the ambient temperature is lower than 50°C.

5. Guaranteed by Relevance.

6. Guaranteed by design.

Function pin description

3V3 (pin 7) Connect this pin to the ATX 3.3V output. This pin provides the output current from the 2V5CLK pin and monitors the power quality. 5VSB (pin 1) provides a well decoupled 5V bias supply for the IC. This pin is connected to the ATX5VSB output. This pin provides the output current from the VSEN1 and VSEN2 pins, as well as the fundamental current of Q2. The voltage on this pin is monitored for power-on-reset (POR) purposes. 5V (pin 18) Connect this pin to the ATX 5V output. This pin provides base bias current for Q1 and monitors power quality. 12V (pin 17) Connect this pin to the ATX 12V output. This pin provides gate bias voltage for Q3, Q5 and Q6 and monitors power quality. Ground (Pin 11) The IC's signal ground. Measure all voltage levels on this pin. S3 and S5 (Pins 9 and 10) These pins change the operating state of the IC from active (S0, S1/S2) to S3 and S4/S5 sleep states. These are the inputs that the digital's internal 50kΩ (typ) resistors pull up to 5 lbs. The internal circuitry removes glitches on these pins for up to 2 microseconds (typically). Additional circuitry prevents any illegal state transitions (eg S3 to S4/S5 or vice versa). Connect S3 and S5 to the SLP-us3 and SLP-us5 signals of the computer system, respectively. EN5VDL (Pin 8) This pin enables or disables the 5V dual output in response to S3 and S4/S5 requests. This is a digital input pin that can only change its state during active state operation or during chip off (SS is below the POR level via an external open-drain device or chip biased to ground). When entering sleep state and following 5VSB POR release or exit shutdown. EN5VDL is an inline high-pass 40µA current source.

FAULT/MSEL (Pin 12) This is a multiplex function pin that allows setting the memory output voltage to 2.5V or 3.3V (for RDRAM or SDRAM memory systems). The internal 40µA current source generates a voltage across the external resistor - this voltage will level with the internal 200mV reference and set the memory regulator output voltage. If any controlled output voltage is too low, on any monitored ATX device, or in an overtemperature event, this pin is used to report a state where the fault is pulled to 5VSB. SS (Pin 16) Connect this pin to a small ceramic capacitor (no less than 5nF; 0.1µF recommended). An internal soft-start (SS) current source, together with an external capacitor, generates the voltage ramp voltage used to control the output ramp. Pulling this pin low with an open drain shuts down all outputs and forces the fault pin low. This C SS capacitor is also used to provide slew rates during active-to-sleep transitions on the controlled voltage 3.3V dual/3.3V SB and 2.5V MEM/3.3V MEM outputs. VSEN2 (pin 20) connects this pin to the memory output (V OUT2). In the sleep state, this pin is regulated to 2.5V through the internal channel to a transistor capable of outputting 300mA (typically). The active state voltage of this pin is passed through an external NPN transistor connected to the DRV2 pin. In all operating states, the voltage on this pin is monitored for undervoltage events.

DRV2 (pin 19) connects this pin to the base of the appropriate NPN transistor. This pass transistor regulates the 2.5V output from the ATX to 3.3V and operates in the active state. 3V3DL (pin 5) connect this pin to the 3.3V dual/alternate output (V out 3). In the sleep state, this pin is regulated to 3.3V; in the active state, the ATX 3.3V output is delivered to this node through an all-pass N-MOS transistor. In all operating states, this pin is monitored for undervoltage events. 3V3DLSB (pin 4)

Connect this pin to the base of the appropriate NPN transistor. During sleep, this transistor is used to regulate the 3V3DL pin connected to 3.3V. DLA (pin 13) connects this pin to the gate of a suitable N-mosfet which, when active, switches the ATX 3.3V and 5V outputs to 3.3V memory, 3.3V dual/3.3V SB and 5V dual output, respectively. 5VDL (Pin 15) Connect this pin to the 5V dual output (VOUT 5). In any working state, the voltage on this pin passes entirely on the MOS transistor. This pin is also monitored for below-voltage events. 5VDLSB (Pin 14) Connect this pin to a suitable P-MOSFET or bipolar PNP. During sleep, the transistor is turned on, connecting the ATX 5VSB output to the 5V dual regulator output.

1V8SB (Pin 3) This pin is the output of the internal 1.8V regulator (V OUT1). This internal regulator is suitable for HIP6503 at 5VSB. Monitor this pin for below-voltage events. 1V8IN (Pin 2) This pin is the input power delivery element for the 1.8V internal regulator. Connect this pin to the 3.3V DUAL/3.3V SB output. VCLK (Pin 6) This pin is the output of the internal 2.5V clock chip regulator (Output 4). This internal regulator only works in the active state (S0, S1/S2) and shuts down in any sleep state, regardless of the chip's configuration. This pin is for monitoring undervoltage events.

illustrate

Operation: The HIP6503 controls 5 output voltages (refer to Figures 1, 2 and 3). It is an applied ATX power supply with 3.3V, 5V, 5VSB and 12V bias input designed for microcomputer. The integrated circuit consists of three linear circuits that provide the computer system's controller/regulator 1.8V SB (V out 1), 3.3V SB and 3.3V auxiliary power supply for the PCI slot (V out 3), 2.5V RDRAM and 3.3V The SDRAM memory power supply (VOUT2), an integrated regulator clock chip (VOUT4) dedicated to 2.5V, provides a dual 5V voltage (VOUT5), and all the monitoring functions required to control and complete the ACPI implementation. Initializing the HIP6503 automatically initializes power when it receives input. A power-on reset (POR) function continuously monitors the 5VSB input supply voltage, enabling 3.3V dual/3.3V SB and 1.8V SB fast soft-start operation after the POR threshold is exceeded. After 3ms (typically) both outputs finish their acceleration, the EN5VDL and MSEL states are locked and the chip continues to ramp up the remaining voltage, as needed. Operational Truth Table EN5VDL pin provides support or disable option 5V dual output in S3 and S4/S5 sleep states. Table 1 describes the truth combinations associated with this output.

Note: Combinations are not allowed.

Internal circuitry does not allow transitions from S3 (suspend to RAM) state to S4/S5 (suspend to disk/soft shutdown) state or vice versa. The only "legal" transitions are active states (S0, S1) to sleep states (S3, S5) and vice versa. Functional Timing Diagrams Figures 4 through 6 are timing diagrams detailing the power response to the enable (EN5VDL) and sleep state pins (S3, and the state of the ATX power supply.

The state of the EN5VDL pin can only be changed when the bias supply (5VSB pin) is below the POR level, or during chip shutdown (SS pin to ground or within 3ms of the 5VSB POR); the state of this changes sleep state The following pins are ignored.

The degumming function used to prevent false sleep state tripping is not shown in these diagrams. The S3 and S5 pins pass through a 2µs filter (typically 1-4µs). This feature is useful in noisy computer environments if the control signal must travel a long distance. Additionally, the S3 pin has a 200µs delay transitioning to sleep. The internal timer is activated once the S3 pin goes low. At the end of the 200 microsecond interval, if the S5 pin is low, the HIP6503 switches to the S5 sleep state; if the S5 pin is high, the HIP6503 enters the S3 sleep state.

Soft-start enters sleep state (S3, S4/S5) The 5VSB POR function starts the soft-start sequence. An internal 10µA current source charges external capacitors. The error amplifier reference input is clamped to a level proportional to the SS (soft-start) pin voltage. As the SS pin voltage transitions from approximately 1.25 volts to 2.5 volts, the input clamp allows for a fast and controllable output voltage rise.

Figure 7 shows a typical application start-up enabled in a sleep state for all output voltages. At T0 5VSB (bias) is applied to the circuit. At time T1 5VSB exceeds the POR level. An internal fasting charge circuit rapidly boosts the SS capacitor voltage by about 1V, and then continues charging with a 10µA current source. The soft-start capacitor voltage reaches approximately 1.25V at time T2, when the 3.3V dual/3.3V SB and 1.8V SB error amplifier reference inputs begin to transition, causing the output voltage to increase proportionally. The upward trend continues until the time when both voltages reach the set value. As the soft-start capacitor voltage reaches around 2.75V, the undervoltage monitoring circuit for this output is activated. The soft-start capacitor quickly discharges to about 1.25V after a 3ms (typical) timeout. Between T3 and T4, the MSEL and EN5VDL options are latched, soft The startup capacitor is designed to ramp up the voltage required for the system for one second. At T5, all voltages are within specification, when the SS voltage reaches 2.75V, all remaining UV monitors are activated and the SS capacitors rapidly discharge to 1.25V reserved for the next transition. Because the 2.5V CLK output only appears when it is active, but instead waits until the main output of the ATX is at regulatory limits.

Soft start into active state (S0, S1) If S3 and S5 are applied at 5VSB, the HIP6503 will assume active state wakeup and hold the desired output for a period of time (usually 25ms) The main output of the application using ATX (3.3V, 5V and 12V) exceeds the set threshold. This pause is necessary to ensure that the main output of the ATX function is stable. The timeout also ensures a smooth transition when the sleep state is supported. The 3.3V dual/3.3V SB and 1.8V SB outputs, whose operation depends only on the presence of the 5V SB, will appear just after the bias voltage exceeds the POR level.

When the output is initially 0V during transition from sleep state to active state (eg S5 to S0 transitions on 5V dual output with EN5VDL=0, or a simple power-up sequence goes directly to active state), memory (3.3V and 5V dual output via The soft-start is pulled high through the body diode of the N channel between these outputs and the 3.3V connected mosfet and the 5V ATX output. Figure 8 shows this start-up case, taking the 5V dual output as an example. When the main ATX output is on, time T0. Due to the +5V boost the 5V dual output capacitor charges Q5 through the body diode (see Figure 3). At time T1, all main ATX outputs exceed the undervoltage threshold of the HIP6503, as well as start the internal 25ms (typ) timer. Soft start at T2 timeout On startup, the 2.5V memory and clock outputs are ramped up, reaching the specified limits at T3. The voltage rises simultaneously with the start of the memory and clock, and at time T2, the DLA pin is pulled high, turning on Q3 and Q5 in the process, and putting 5V dual output regulation. Shortly after T3, as the SS voltage reaches 2.75V, the soft-start capacitor acts to rapidly discharge to around 2.45V until a valid sleep state request is received from the system.

Fault Protection All outputs are monitored for undervoltage events. One due to any output, in turn, causes a sudden drop in that particular output. If any output voltage falls below 80% (typ) of its set value, the event is caused by pulling the fault/MSEL pin to 5V. Additionally, exceeding the maximum current rating of the integrated circuit's regulator (the output of the on-chip bandpass regulator) can cause the output voltage to sag; if too large, this sag can eventually trip the undervoltage detector and signal a fault to the computer system . A fault condition that occurs at the output while controlling passes through an external pass transistor only triggers the fault flag, it does not close or lock the circuit. When the output is controlled by an inter-pass transistor, the fault flag will be triggered, which will turn off the corresponding fault-only regulator. If the closure or latching of the entire circuit should fail, for whatever reason, this must be accomplished by externally pulling or locking the SS pin. Pulling the SS pin low will also force the fault pin low and reset any internally locked outputs. Special consideration is given to the initial boot sequence. If after a 5VSB POR event the 1.8V SB or 3.3V dual/3.3V SB outputs are boosted at the control voltage, then the fault output goes high and the entire IC latches off. The latch can reset the condition by cycling the bias supply (5V SB). 1.8V SB and 3.3V Dual/3.3V SB output at any other time as described in the second paragraph under the current heading. Another condition that can trigger a fault flag is excessive die temperature. If the HIP6503 reaches an internal temperature of 140°C (typical), the fault flag is set, but the chip continues to operate until the temperature reaches 155°C (typical), unconditional shutdown of all outputs occurs. Operation was resumed at 140°C and temperature cycling continued until the failure was removed.

In a HIP6503 application, the loss of any one of the active ATX outputs (3.3V", 5V", or 12V"; via the onboard voltage detection monitor) during active state operation causes the chip to switch to the S5 sleep state, in addition to reporting an input UV fault/ State of the MSEL pin. Leaving this forced-S5 state can only be achieved by returning the fault input to a voltage above its UV threshold, removing the 5V SB bias voltage by resetting the chip, or placing the SS pin at a potential below 0.8V. Output Voltage The output voltage is set internally and does not require any external components. The select voltage for the V MEM memory is achieved through an external resistor connected between the FAULT/MSEL pin and ground. An internal 40µA (typical) current source creates a voltage drop across this resistor. Every 3.3V SB boost or chip reset (see soft-start circuit), this voltage is locked with the internal reference and settings. Based on this comparison, the output voltage is set to 2.5V (RSelect=1kΩ) or 3.3V (RSelect=10kΩ). It is important that no capacitors are connected to the FAULT/MSEL pin. The presence of capacitive elements on this pin may result in incorrect memory voltage selection. See Figure 9 for details

Application Guide

The 5VSB output of a typical ATX power supply is capable of 725mA between soft-start intervals. When powered up in sleep state, it needs to provide enough current to charge all output capacitors and at the same time provide some current load to the output. Drawing too much current from the 5VSB output of ATX can cause a voltage collapse and cause a pattern of continuous restarts, to the behavior or health of the system. A built-in soft-start circuit provides tight control of the slew - HIP6503 controlled acceleration of the output voltage, making the UPS immune to brownout events. Since the output increases linearly, the current dedicated to charging the output capacitor can be calculated as:

I SS - Soft-Start Current (Typically 10µA) Soft-Start Capacitor V BG - Bandgap Voltage (Typically 1.26V) (C OUT x V OUT ) - Sum of the product between Capacitance and Output Voltage (total charge delivered All outputs) Due to various system timing events, a soft-start interval of no more than 30ms is recommended.

closure

All HIP6503's can be turned off by pulling the SS pin below to the specified shutdown level (typically 0.8V), open drains or capable of sinking at least 2mA in the event of a situation that could compromise the computer system, or at any other time. Low-pull stainless steel pins effectively shut off all delivery elements. After releasing the SS pin, the HIP6503 performs a new soft-start cycle and resumes normal operation according to the ATX power and control pins.

Layout Considerations

A typical application using the HIP6503 is direct implementation. Just like other linear regulators, attention must be paid to a small number of potentially sensitive small-signal components, such as to sensitive nodes or nodes that provide critical bypass currents. Power components (through transistors) and controller ICs should come first. The controller should be placed in the center of the motherboard as close to the memory load as possible, but not too far from the clock chip or the processor. Insured connections for 1V8SB, DRV2, and VSEN2 are appropriately sized to carry significant resistive losses of 250mA; similar guidelines apply to the VCLK output, which can output up to 800mA (typ). Since the VCLK output current is 3.3V supplied by ATX, the connection from the 3V3 pin to the 3.3V plane should be sized to carry the maximum clock output current while exhibiting negligible voltage loss. Likewise the 5VSB and 5V pins are current - for best results, make sure they are with their respective sources identified by appropriately sized traces. This power-on transistor should be placed to dissipate heat to match the power dissipation of the device. Where? Applicable, multiple vias connected to large inner planes can significantly reduce local device temperature rise. The placement of decoupling capacitors and bulk capacitors should follow a location that reflects their purpose. Therefore high frequency decoupling capacitors should be placed as close to the load as possible, they are separate; those that decouple the controller from the controller pins are near the load connector or the load itself (if embedded). Even though the placement of bulk capacitors (aluminum electrolytic or tantalum capacitors) is not as important as the placement of high frequency capacitors, it is better to keep these capacitors close to the load they serve. Key small-signal components include the soft-start capacitor, C SS, and the memory select resistor, R Select. Place these parts close to the corresponding pins of the control IC and place their ground close to the ground pad through a via. Minimize leakage current paths from these nodes as the internal current source is only 10µA (10µA to 40µA).